Interview Questions for ASIC

Dear Readers,

Here I would like to post some of the interview question which I have discussed with some senior engineers and industry experts. These are the questions most of the time interviewers asks. Here I will try to explain those all.

Que 1. What is setup and hold time? What will happen if there is setup and hold time violation?
[This question can also asked like "what is metastable state or what is metastability?"]

Ans 1.
Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.

Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

Que 2. What is the difference between latch and flipflop?
[This is the very basic question that most of the interviewer would like to ask to check basic fundamental of digital electronics]

Ans 2.
The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.

Que 3. Build a 4:1 mux using 2:1 mux
[This is also a very basic question most interviewer would like to ask]

Ans 3. I would try to explain
Let say we have three 2:1 mux called A'B and C, So here we use two inputs of mux A and two input of mux B (total 4 input, which is the requirement to build 4:1 mux) and output of these two mux (A and B) will be 2 lines which will be input for third mux C. So we will be having 1 output from mux C. Now remaining thing is select line. We will hard wired selection line of A and B and called it as S0 and one select line will be used for mux C called S1. This way we can make a 4:1 mux using 2:1 multiplexer.

Que 4. Implement an AND gate using mux.

Ans 4. For AND gate give one input as select line. Incase if you are using B as a select line connect one input to logic 0 and one input to A.

Oue 5. In pure combinational Ckt, its necessary to mention all the inputs in sensitivity list? Is yes, Why?
Ans 5. Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch.

Hope this questions and answers are useful for the interested readers.

Happy Reading,
ASIC With Ankit

JEDEC has announced eMMC4.4 standard

Dear Friends,

Here I would like to inform you regarding the Multimedia Card's new version specification as JDEC has now announced 4.4 on 14th April 2009. I am very excited to read the specification. I know now you might be surprised why I am so excited to read the same. The reason is I worked on verification of eMMC4.3 card IP.

JEDEC Announces Publication of new MMC v4.4 specification

* New Standard Features Performance and Security Features for Embedded Mass-Storage Flash Memory
* Widely Used in Mobile Phones, GPS, MP3 Players and Other Portable Electronic Devices

ARLINGTON, Va., USA – April 14, 2009 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD84-A44 MMC Version 4.4 standard. Continuing the evolution of e.MMC as an industry-leading memory technology, the new standard offers designers numerous enhancements including a doubling of the memory interface performance, flexible partition management and improved security options.

You can find this article from below given link:

From this link you can also download the standard specification provided by JDEC.

Hope this is useful information for interested readers.

ASIC With Ankit

Seminar at NMG Polytechnic (ASIC with Ankit)

After a long time I got chance to represent myself as an presenter of technology in front of engineering students. As I have been in this field from more than 3 years I was exited to share my experience and importance of technology to the engineering students.

As I have finished my Diploma Engineering from N.M.G.P Institute (An ISO 9001:2000 certified), Kanara, Ranpur, I was planing to share my experience on technology in front of NMGP students and that's what I did in last week. It was thursday 2nd April when I suppose to go to NMGP for seminar on 'VLSI' and 'Importance of individual EC subjects in field or industries'.

I went there (NMGP) thursday morning with my power point presentation on my Lappy. As seminar timing was around 11:00 am, I had a time to visit NMGP building and recalled my old memories. I spent some time with old staff members and respected lectures who are still working with NMGP. At 11:00 am Seminar hall was ready with projector and my laptop setup. Students were also ready, taken their place and waiting for my presence on the stage with excitement !! I was too excited since it was my first presentation in front of 100s of engineering student !

I have started my presentation in front of EC engineering students and Sr/Jr Staff members (Lectures) of EC department. Agenda of that seminar was to give overview of VLSI technology and Importance of Digital Electronics in Industries. The goal was to create some interest for students on Digital fundamentals keeping in mind the industries requirement and technology growth !

Dear Readers,

Here I would like to share my some experience on my first seminar given to the polytechnic collage where I did my Diploma studies.

I was a student of the this polytechnic and I know most of the student's goal is to get good marks in the examination. But what I realized at this point is apart from mark there are something which each students should understand which is more important when you go for Job.

I explained the importance of Digital electronics in Chip Design and Verification. I have also explained latest VLSI Chip Technology with Transistor fundamentals by some examples and snap shots of some Chips. With this presentation I was trying to create self inspiration and motivation for engineering students. What I believe is "If you do things with your interest, things will be very easy and you can do it with smooth way".

Most interesting stuff of the seminar was two technology on which I worked in my past 1. USB OTG (USB On The Go) and 2. eMMC (Embedded Multimedia Card) Card IP (Intellectual Property) Verification. I have explained the application of those two technology and it was really interesting for students because they didn't know about these. I was glad after sharing this technology to students. Thanks to all those students who attended my session. It was full of excitement with lots of basic question answers session with students !

I hope with my efforts of presentation, some students might have started improving interest on engineering subjects, skills etc.... I have been receiving a many questions from students and answering their questions which could help them move ahead with their career. I would eagerly waiting to see somebody as an ASIC Engineer after some year down the road.

Thanks to NMGP Management, Sr/Jr Staff Members, Lecturers and students for their support and co-ordinations.

Visit their website ( for Institute details.

ASIC with Ankit