Thursday, May 23, 2019

System Verilog Assertions (SVA) – Types, Usage, Advantages and Important Guidelines!

Dear Readers,


There was an article published by SmartPlay Technologies back in 2015 when I was working with them. It has very useful information to understand the usage, advantages, and guidelines about System Verilog Assertions (SVA).

ASICs continue to grow in size and complexities and in this case, traditional verification techniques are not sufficient to achieve verification confidence. In complex designs, debugging simulations is an ever-increasing challenge. To address these challenges assertion-based verification is found. Design and Verification engineers can place assertions in design or bind to design which will be useful to monitor, report and take action when incorrect behavior is detected. Assertions are playing a major role in test bench development which helps to achieve maximum confidence on bug-free design. Moreover, it can be used in simulations as well as in formal verification. It enables engineers to leverage the strength for block level, subsystem level and for chip level verification in order to reduce the overall effort and efficient verification closure. System Verilog Assertions are setting up a viable and effective standard in design and verification. An assertion adds an advantage in the debugging process and makes complex simulation debug easy.

The introduction of SVA added the ability to perform immediate and concurrent assertions for Design as well as for Verification. Assertions are used to validate design whether it is working correctly or not. Assertions can be useful to make sure ‘How good is the test case?’ Furthermore, it provides a means to measure the quality of the verification process through the creation of coverage using cover property feature of System Verilog assertion.
Questions are 


1. What type of System Verilog Assertions we have?
2. Where to put these assertions in our test bench development? 
3. How to implement these assertions?
4. Usage, Advantage
5. What are the important Guidelines for SVA implementation?

To find more details please read this blog post "System Verilog Assertions (SVA) Types, Usage Advantages and Important Guidelines" 

Thanks,
Ankit

Wednesday, January 2, 2019

Happy 2019!!


2019 has finally arrived like every new year. A new year always bring new challenges in many fields which will allow us to learn and grow even more!! Best wishes on this new year from us!

This time of the year is filled with moments of celebration, reflections, and resolutions- all of which are great for inspiration and making the necessary changes one has been thinking about in the past year. It is also the time to assess the year that has passed. So what happened during 2018 and what to do for a new year?

Lets all step back and self evaluate our self and list down all positive things that we think we are stronger and also list down weak points where we think we are lagging behind. Let's all try to focus on our weak areas and improve those. On this new year, let's all take some action items to work on and focus on improvements. I wish you all a happy new year, may this new year brings lots of energy to do more and more good things. 

Everybody expects life to have smooth way, nobody expects their life to have painful bumps like a 'ROLLER COASTER'! Things may go wrong in life, everything is up and down in life. Every year has new challenges and opportunities with lots of fun, learning !! Like every year this year was also an awesome year together. Let’s all step back for a few moments and think, list down all major good/bad events occurred to individual’s life. I must say… every event would teach you something to learn and accept a few things.. whether it is good or bad. Good events teach you how to share, celebrate and enjoy quality time while bad events teach you even more… like how to react, fight bad time, learn, accept and how to move forward with positivity. I strongly believe It’s a matter of how you look at it together.

Everyone has their own learning and experience from the past year and new thinking, the expectation from the new year! Like everyone we also learn many things nice way while some hard way….. but you learn in any case!

I wish new year would be 1000 time better than the past year for everyone! May this year brings lots of happiness and energy to do more and more good things for family, friends, and society.

Wishing you all very happy and healthy new year!!

With Love,
ASIC With Ankit