Sunday, September 23, 2018

System Verilog UVM Callbacks: Development and Usage

What is callback? If you know System Verilog, Easily explainable example is post_randomize() method which allows users to execute logic after an object has been randomized.
Callbacks are pre-defined hooks that allow users to influence a verification environment from outside the environment.

The UVM callbacks allow reusable environments to define our own hooks for our application needs. The main advantage of a callback is the ability to combine multiple extensions that are created by multiple teams into a single testbench.

How to Define Callbacks?

First thing, verification engineer to decide is to an interface to make available. Let’s take an example. Say for example you want to add a callback to modify a data packages after it is randomized. This can be implemented as below:


Second thing, we need to do is to register the callback type with the type that will use the callback. This registration enables UVM to do type checking when a user tries to add a callback to a specific object.


If you miss the registration, UVM issues a warning that the callback type was not registered with the object type.

Now, let’s understand how you insert the callback.
We will now insert a call to the callback functions in the code, UVM provides a utility macro to make the process very easy.


How to use Callback?

Now we have callback class defined and can be used as necessary in the testbench to modify the generated data before its driven on DUT. Now, let’s see how we use it in the test bench.


Once this is done, you need to attach the callback to a specific instance from your test case and then run a test. With this implementation when you run your simulation, this callbacks will update/modify randomized packets before driver drives it to the DUT signals.

This type of mechanism is useful in many places such as for error injection, data corruption, missed transaction etc…

Happy Reading,