Saturday, December 20, 2014
What a 'logic' you have System Verilog !!
Before we understand the “logic” data type for system Verilog, Lets understand verilog data types “reg” and “wire”. Wire is used to connect gates or modules and are physical wire in a circuit and it must be driven by a continues assignment statements. “Reg” in Verilog is a data object that holds its value from one procedural statement to next. When we say "reg (register datatype)" it does not mean the register in the hardware or a physical register in circuit. This is the common mistake or assumption mostly engineers thinks while learning Verilog.
In System Verilog, it improved the classic “reg” data type so that it can also be driven by continues assignments. The name they given for data type is “logic” in System Verilog. It is 4 state (1, 0, X, Z) System Verilog data type.
Let’s take an example to understand the usage of logic data type
module Asic_With_Ankit (input logic xyz);
logic a, b, c;
a = 0;
forever #(DELAY/4) a = ~a
assign c = ~c;
In above example, you can see statement “a = 0” is procedural assignment while statement “assign c = ~c” is a continues assignment. So the important point to understand here is “SV allowed continuous assignments to logic variables, whereas in Verilog, you can’t use continuous assignments to “reg” variables”
“logic” signal can be used anywhere a “net” used but there is one exception to this, you can not drive logic variable from multiple driver. In these type of cases, variable needs to be a net type such as “wire” so that SV can resolve the multiple values.
Logic type can only have a single drive, it can’t allowed multiple driver. This means we can declare all signal as logic to find if is there any multiple driver issue. Because in this case you should be able to see compilation issue if there is any multiple driver by declaring all signal with type “logic”. Of course for the signal you would like to have multiple drivers shall be declared as net type such as “wire” or “tri”.
So, logic data type is identical to “reg” in every way except in SV it improved reg with logic so that it can also be driven by continues assignment and there would not be any confusion on “reg” data type w.r.t to physical register in hardware J
ASIC With Ankit
Posted by Ankit Gopani at 8:38 AM
Working as a Lead Design Verification Engineer. As an ASIC Verification Engineer, we basically provide verification solutions to our customers for verifying their Intellectual Property and complex SoCs.The verification phase is divided into many forks like feasibility study for Specification and requirements, Design and Verification and finding bugs in Designs, review phase at each and every level. I pursued Diploma in E.C, B.E in Electronics and Communication and MBA in software project management. -ASIC With Ankit