PASS and FAIL Messages with Colors...!

How many among you know that you can actually display color messages using Verilog and SystemVerilog?

You can implement a logic in your testbench to have nicely colored display messages at the end of your simulation which will give you a PASS/FAIL messages. I have written a piece of code given below and you can refer the same. I have captured a snapshot of output which you can see at the top.

program clr_display();
class color ;
   task display ();
      $display("*********** TEST CASE PASS ************");

      $display("*********** TEST CASE FAIL ************");

initial begin
   color clr;
   clr = new ();
   clr.display ();

With an above example you can have a display messages with colors. So this way you can have nicely and colored messages on your terminal.

ASIC with Ankit


Nilay Goyal said...

Thats cool! does this work for all simulators viz. IUS, VCS and Questa...?

Ankit Gopani said...

Thanks Nilay,

For Questa and VCS it is working and I am sure it will work for IUS as well but have not tried it with IUS.

-ASIC with Ankit

Narendra Patel said...

Yes it too works with Incisiv irun or IUS.
Ankit, I've one more concern. I could see colored messages in console however not in log file when we open log in editor (I use gvim here).
In short, is it possible to get these colored messaged in log too? If any gvim syntax available with you please share.
I do search on google but not succeeded yet.

Appreciate your help!!


Narendra Patel said...
This comment has been removed by the author.
Ankit Gopani said...

Thanks Narendra for trying it on IUS..

Well, I dont have any gvim syntax available for the same thing.. but will let you know if I come across anything.. !