Tripple Equality operator is not supported in constraint, or in VCS ?

Dear All,

I have been playing with the constrains and and randomization from last couple of years and come to know one thing while using the "thipple equality operator in constraint".

I have posted some interesting stuff on equality operator in my previouse blog called "what should we use == or === ??" One more interesting thing I came across with this operator is, 'These ('===' and '!==') operators are not allowed in System Verilog Constraints in VCS'. I am not sure about the other tools. I would be eager to know whether its a limitation for tool or its an constraint limitation in System Verilog?

I have gone through the LRM and could not able to find this limitation for constraint..!

If you use tripple equality operators in consraints then you will find the compilatin error given below:

Error-[IUORCE] Illegal operator in constraint
The operator !== is not allowed in constraints.
Remove the operator or replace it with an expression allowed in constraints.

Seems interesting...! I am eager and would be pleased to hear some thing on this, suggestions and inputs are always welcome....

Happy Reading,
ASIC With Ankit


Dhaval said...

Ankit Da,

RNG engine works on 2-state logic only.
Do you remember any case where your RNG engine generate x or z? Never. thats why.


Ankit Gopani said...

Hey Dhaval,

Thanks for the answers. I agree with your answer as I have never seen RNG engine to generate x or z, so may be this the reason why constrains does not need tripple equality operator.

Thanks for sharing your knowledge.


Chander Makhija said...

Dhaval at all,
Well you are right here.

Adding more,
RND Engine wont work to generate x and z but u can always constraint 4 state variables, which will generate 2 state values for that 4 state variable.