Assertions : What a powerfull feature of System Verilog..

Dear Readers,

SystemVerilog Assertions (SVA) are getting lots of attention in the verification community: Assertions are primarily used to validate the behaviour of a design. They may also be used to provide functional coverage information for a design..!

There are two types of Assertions in System Verilog :
1. Immediate Assertion
2. Concurrent Assertion

Both types have their own strong features, That all depens on our requirement which will decide which type of assertion we should use in our environment. But friendly speaking I would prefer Concurrent assertion most of the time as I found some of the advantages compare to Immediate assertion. And those advantage always encouraged me to use this type of assertions. Here I am listing down the advantages as per my experience:

1. Coverage statements (cover property) are concurrent and that's the reason we have used concurrent assertion as a part of our Test Bench. So it will be easy to dump a final coverage using this type of assertion with the strong System Verilog feature

2. The implication construct (|->) allows a user to monitor sequences based on satisfying some criteria, e.g. attach a precondition to a sequence and evaluate the sequence only if the condition is successful. There are two forms of implication: overlapped using operator |->, and non-overlapped using operator |=>.
3.User can use sequence to build complex properties.

These are the advantages which I came across so far in my experience on Assertions. I would be pleased if somebody can provide advantages of Immediate Assertion over Concurrent Assertions.

Assertions are providing strong verification features with which verification engineer can confident on his verificatoin environment and coverage using cover property with concurrent assertions.

Now you must be having a question that how assertions are effective with System Verilog?

In Verilog complex check requires complex verilog code, which will appear to be a part of RTL model to a Synthesis compiler, and one more disadvantage with Veriog is Assertion will active through out the simulation there is no simple way to disable all or some of the assertion during the simulation which is there in System Verilog, Now you should realize how effective it is Right ....? Means Asserstions can be controlled using system Verilog during the simulation.

One more strong feature which I have used is Assertion Binding, which is unique and powerful feature of System Verilog. Using this feature you can have your all assertion defined (coded) in separate TB file where you can have all required DUT as well as TB signals and registers with hierarchically from Top file. So that means without touching the RTL we can write assertion in separate file and that file will be included in our Test Environment.

As a Verification Engineer, I like Assertion, its strong and powerful in terms of Verification.

I would be pleased and thankful to you if you can share your experience on Assertions.

Happy Learning,
ASIC With Ankit


Jay Panchal said...

Nice Stuffs....

Ankit Gopani said...

Hey Jay,

Thanks for reading.