Wednesday, January 2, 2019

Happy 2019!!

2019 has finally arrived like every new year. A new year always bring new challenges in many fields which will allow us to learn and grow even more!! Best wishes on this new year from us!

This time of the year is filled with moments of celebration, reflections, and resolutions- all of which are great for inspiration and making the necessary changes one has been thinking about in the past year. It is also the time to assess the year that has passed. So what happened during 2018 and what to do for a new year?

Lets all step back and self evaluate our self and list down all positive things that we think we are stronger and also list down weak points where we think we are lagging behind. Let's all try to focus on our weak areas and improve those. On this new year, let's all take some action items to work on and focus on improvements. I wish you all a happy new year, may this new year brings lots of energy to do more and more good things. 

Everybody expects life to have smooth way, nobody expects their life to have painful bumps like a 'ROLLER COASTER'! Things may go wrong in life, everything is up and down in life. Every year has new challenges and opportunities with lots of fun, learning !! Like every year this year was also an awesome year together. Let’s all step back for a few moments and think, list down all major good/bad events occurred to individual’s life. I must say… every event would teach you something to learn and accept a few things.. whether it is good or bad. Good events teach you how to share, celebrate and enjoy quality time while bad events teach you even more… like how to react, fight bad time, learn, accept and how to move forward with positivity. I strongly believe It’s a matter of how you look at it together.

Everyone has their own learning and experience from the past year and new thinking, the expectation from the new year! Like everyone we also learn many things nice way while some hard way….. but you learn in any case!

I wish new year would be 1000 time better than the past year for everyone! May this year brings lots of happiness and energy to do more and more good things for family, friends, and society.

Wishing you all very happy and healthy new year!!

With Love,
ASIC With Ankit

Friday, November 9, 2018

Happy Diwali & Prosperous New Year!

Diwali is the biggest and the brightest festivals celebrated by families around the world. Deepavali (actual name of Diwali) means "a row of lights." This auspicious day is also known as the "festival of lights. There is a saying “A Happiness can be found from darkest of dark if one knows how to switch on the light”! 

The evil need not necessarily come in the form of demons, it can come as depression, desperation, and frustration which can cause more damage. Diwali is a reminder to slay all that is negative to our life. 

There is so much happening during this whole week, people start preparing for Diwali, shops (e-shops J) are full of sales and there is light all over. People celebrate Diwali with many other things like firecrackers, visiting friends and family places and having lots of sweets! Well, I miss those days celebrating Diwali with lots of firecrackers and lights on streets with friends. A lot of regulation here, but still we manage to celebrate with some of the crackers in our patio J One of these years, I am going to take a vacation to celebrate Diwali back hometown to renew my Diwali spirit. On Diwali days, people use to do colorful rangoli at their house.

Diwali is one of the biggest and brightest festivals in India and we do celebrate it with full of enthusiasm and happiness. I would like to celebrate this Diwali by expressing thanks to all my friends, family members, near and dear ones! You all are awesome and I am lucky to have you all in my life. 

Diwali is the last day of Gujarati Year, Today, Vikram Samvat 2075 begins. So wishing you all a Happy New Gujarati Year. May this new year come with lots of happiness in your life.

May This Diwali be as bright as ever and brings joy, health, and wealth to you and your family. May this Diwali bring you the utmost in peace and prosperity. We wish you all a Happy Diwali and a prosperous new year!

Happy Diwali & Happy New Year!
ASIC With Ankit

Sunday, September 23, 2018

System Verilog UVM Callbacks: Development and Usage

What is callback? If you know System Verilog, Easily explainable example is post_randomize() method which allows users to execute logic after an object has been randomized.
Callbacks are pre-defined hooks that allow users to influence a verification environment from outside the environment.

The UVM callbacks allow reusable environments to define our own hooks for our application needs. The main advantage of a callback is the ability to combine multiple extensions that are created by multiple teams into a single testbench.

How to Define Callbacks?

First thing, verification engineer to decide is to an interface to make available. Let’s take an example. Say for example you want to add a callback to modify a data packages after it is randomized. This can be implemented as below:

Second thing, we need to do is to register the callback type with the type that will use the callback. This registration enables UVM to do type checking when a user tries to add a callback to a specific object.

If you miss the registration, UVM issues a warning that the callback type was not registered with the object type.

Now, let’s understand how you insert the callback.
We will now insert a call to the callback functions in the code, UVM provides a utility macro to make the process very easy.

How to use Callback?

Now we have callback class defined and can be used as necessary in the testbench to modify the generated data before its driven on DUT. Now, let’s see how we use it in the test bench.

Once this is done, you need to attach the callback to a specific instance from your test case and then run a test. With this implementation when you run your simulation, this callbacks will update/modify randomized packets before driver drives it to the DUT signals.

This type of mechanism is useful in many places such as for error injection, data corruption, missed transaction etc…

Happy Reading,

Wednesday, August 9, 2017

UVM Sequencer and Driver - Basic concept

A sequencer is an advanced stimulus generator that controls the items provided to the driver and then driver executes those items during the simulation.

Generator randomizes arrays of transactions and sequencer controls the generation of random stimulus by executing sequences. The sequence has the meaningful stream of transactions which can contain random data items, parameters and user can also add constraints. A user can combine sequences to create complex traffic streams.

Now, let’s understand UVM Sequencer with some more details from very simple picture given below:

Typically sequencer waits for get_next_item() call from a driver, randomize the item data and then sends the data item to the driver for execution.

How to create a sequencer?
  • Derive sequencer from the uvm_sequencer base class and specify request and response type prameters.
  • Use `uvm_component_utils and constructor

With these, you can define the baseline for sequencer, with built in sequencers behavior you can generate a constrained random data with synchronizing driver and sequencers.

Driver and sequencer are connected by way of TLM with driver’s seq_item_port connected to the sequencer’s seq_item_export. Sequencer produces data and sends them through se_item_export and driver consumes data itesm through its seq_item_port as shown in the figure above. A response is optional. Connections are made by components that contain instances of the driver and sequencers.

Handshake between Driver and Sequencer:

Basic handshake is done using the task get_next_tem() and item_done(). Driver requests a randomized item from sequencer and block waiting for the sequencer to have an item available. When sequencer has an item available, it will provide it and the get_next_item() task will return this item. Driver signals the sequencer that the item was processed using item_done() after sending it to DUT.

Simple Example:

class my_sequencer externs uvm_sequencer #(my_pkt_transfer);
 `uvm_component_utils (my_sequencer)
   function new (string name, uvm_component parent); (name, parent);
   endfunction : new

end class : my_sequencer

Let's understand sequencer from example sudo code:

`uvm_component_utils macro is used to register sequencer with the common factory. In the class definition above, by default, the response type is the same as the request type. If you expect the different response, an optional second parameter must be specified for the uvm_sequencer.
something like...

class my_sequencer externs uvm_sequencer #(my_pkt_transfer, my_pkg_response);

These are basic things to understand sequencer and definition of the sequencer to use it with the driver. We will continue on this for driver part and communication with Driver.

Hope, this is useful and clears some basic facts about sequencer and its usage. Feel free to shoot me an email for any question on this or would like to understand more on this.

Happy Reading,

Monday, November 23, 2015

System Verilog Assertion Binding - SVA Binding

Dear Readers,

As we all know SV has become so popular in verification industry with its very good features and constructs which helps us verify today's complex designs. Today, I am going to discuss about SVA binding that we use in test bench for SVA properties.

There are VHDL and Verilog model we use to deal with these days. Mostly verification engineers are not allowed to modified these modules. But still SVA addition to these modules are required and easy to verify lot of RTL functionality. How can you add SVA to these modules? 

Here is where system verilog ‘bind’ comes in picture. Generally you create a SVA bind file and instantiate sva module with RTL module.

SVA bind file requires assertions be wrapped in module that includes port declaration, So now lets understand this with a small example to understand basic things on  how to use SVA bind : 

click on below image to enlarge.. 

DUT_Module - Dummy RTL module to understand this example
SVA_Module - Dummy SVA module with implemented assertion property
TB_Module - Dummy test bench code to see how bind works with module instantiation 

Here, you could see there is DUT instantiation created DUT_u1 instance of DUT_Module. Now point of interest for us would be, how to bind DUT instance to SVA module.

To understand this take a look at line number 50 in image from TB_Module, where you could see 'bind' keyword used with DUT_Module module and SVA_Module. This is the place where we are binding DUT module with SVA module. Thus passing DUT signal information to SVA module. With this we could play around with DUT signal and can check assertion properties using DUT signals available through this instantiation.

If the assertion module uses the same signal names as the target module, the bind file port declarations are still required but the bind-instantiation can be done using the SystemVerilog .* implicit port connections. If signal names are not exactly matching between target and bind file module then we need to expand the instantiation with respected port names.

Hope, this information on SVA binding is useful, stay in touch with me and share your views !


Monday, March 9, 2015

System Verilog : Functional Coverage Guidelines

We have been implementing every possible checks to make sure design is verified but what have we done to check our test bench ? How do we make sure that our test bench has covered everything that needs to be covered w.r.t to specification and test plans ? Here is the place “Functional Coverage” and “SVA” comes in picture!

Before we start on few guidelines to follow while working with functional coverage, I would encourage you to refer various posts on functional coverage and assertions to get high level idea on architecture and usage. Click on 1, 2, 3!

Now, Basic questions can come to mind is, "what is the difference between code and functional coverage?". Let’s understand it at high level and then we will move forward to understand guidelines for functional coverage.

Sr No

Code Coverage

Functional Coverage  and SVA


Derived from design code with the help of simulation tools

It is user specified, controlled approach coverage by test bench


Evaluate design code to check whether structure is covered or not

Measures functionality part with the help of covergroup, cover point and bins (with the help of luxury feature of System Verilog J)

(With SVA you can capture functional coverage using cover property)

To conclude with few guidelines from various posts on functional coverage and assertions:

Functional coverage and code coverage both are contributing highly on sign off criteria for verification. Verification engineers have to make sure that their test plan and test environment is intelligent enough to satisfy the code/functional coverage closer. Code coverage is generated by tool with the help of the simulations generated by the test environment. So test environment should be random and intelligent enough to make sure design is covered as a part of code coverage and designer should be in agreement while code coverage review. There should be valid comments with reason for all exclusions for code coverage w.r.t to design specification. Functional coverage should be written such a way that it should be able to capture all identified functionality while defining the test plan. Coverage and assertions are very important entity in the verification process and there are few guidelines that would help in verification process.

Few guidelines while working with functional coverage
  1. Your test plan should be based on the functionality you want to verify w.r.t to specification
  2. You should have a coverage matrix with the list of cover point details w.r.t to your test plan scenario and there should be link of traceability between test scenario and cover point.
  3. Environment should have control mechanism for enabling or disabling coverage and assertions for better control ability in your environment
  4. Don’t enable functional coverage at the beginning of the verification to avoid simulation overhead in the starting phase of verification
  5. During the initial time of the verification bug ration is typically high, as you move forward to the verification bug ration would start to drop. Here is the time when you should enable coverage and analyze it
  6. Functional coverage plan needs to be updated as verification progresses
  7. As your knowledge of the design and corner case understanding increases, you should keep updating your functional coverage plan
  8. Make effective use of cover group “trigger” and sampling mechanism. (Stay tune for sampling mechanism on upcoming blog post !)
  9. Follow meaningful names of cover group and cover points. This will help when you in debug process
  10. Coverage should not be captured on failing simulations. Make sure to gathered coverage for only passing simulation. If few tests are not passing in regression first make sure to fix those issues before come to a conclusion on coverage achievement
  11. If your tests are keep exercising the same logic in design, start developing the new tests for uncovered coverage part of coverage (coverage holes)
For guidelines on SVA, please refer to this article !

Stay tuned to understand functional coverage sampling mechanism !

ASIC With Ankit

Saturday, December 20, 2014

What a 'logic' you have System Verilog !!

Before we understand the “logic” data type for system Verilog, Lets understand verilog data types “reg” and “wire”. Wire is used to connect gates or modules and are physical wire in a circuit and it must be driven by a continues assignment statements. “Reg” in Verilog is a data object that holds its value from one procedural statement to next. When we say "reg (register datatype)" it does not mean the register in the hardware or a physical register in circuit. This is the common mistake or assumption mostly engineers thinks while learning Verilog.

In System Verilog, it improved the classic “reg” data type so that it can also be driven by continues assignments. The name they given for data type is “logic” in System Verilog. It is 4 state (1, 0, X, Z) System Verilog data type.

Let’s take an example to understand the usage of logic data type

Example :

module Asic_With_Ankit (input logic xyz);

   parameter DELAY;
   logic a, b, c;

 initial begin
    a = 0;
    forever #(DELAY/4) a = ~a

  assign c = ~c;


In above example, you can see statement “a = 0” is procedural assignment while statement “assign c = ~c” is a continues assignment. So the important point to understand here is “SV allowed continuous assignments to logic variables, whereas in Verilog, you can’t use continuous assignments to “reg” variables”

“logic” signal can be used anywhere a “net” used but there is one exception to this, you can not drive logic variable from multiple driver. In these type of cases, variable needs to be a net type such as “wire” so that SV can resolve the multiple values.

Logic type can only have a single drive, it can’t allowed multiple driver. This means we can declare all signal as logic to find if is there any multiple driver issue. Because in this case you should be able to see compilation issue if there is any multiple driver by declaring all signal with type “logic”. Of course for the signal you would like to have multiple drivers shall be declared as net type such as “wire” or “tri”.

So, logic data type is identical to “reg” in every way except in SV it improved reg with logic so that it can also be driven by continues assignment and there would not be any confusion on “reg” data type w.r.t to physical register in hardware J

ASIC With Ankit

Tuesday, November 11, 2014

System Verilog Class : No numbers for class name please !

Dear Readers,

Today I am going to share you one limitation with system Verilog class definition. We know Class is the basic feature to understand if we have to learn System Verilog. Class is the basic construct, data type in System Verilog. Some of the class feature I highlighted in my couple of previous blog posts can be found from here and here.

Methodological approach to name system Verilog class and major advantages

As a verification engineer with a mindset of methodological test bench architecture we prefer to name all data types, variables, blocks with meaningful names and their objects so that anybody with little understanding of that environment will be easily able to understand why is that class defined or what is the significant of adding this parameter? Let me give you a small example:

For example, a team of 3-5 engineers have developed a complex SoC or Block level verification environment using system Verilog. Environment is such complex that it has many classes defined to perform certain functional verification. Now with methodological approach usually engineers defined their test environment by classifying various configurable parameters and feature control and transaction based features and they will develop environment to accommodate these features in respected class called configuration class and transaction class respectively. They have given a names for cfg and transaction class to “rx_dma_cntrl_cfg” and “rx_dma_cntrl_tr”. Here “_cfg” represents configuration class while “_tr” represents transaction class which is quite common approach in today’s test bench developments.

Why do we need to follow these type of small-small things?

Well, answer to this question is “there are many advantage of following these type of approach while developing your test environment at the same time it does not cost you much”

  1. It helps in debugging the complex test environment as we all know “debugging is not free” and it always consumes amount of time and bandwidth in the verification cycles but we can always try to reduce the debugging efforts by following these small steps.
  2. Helps engineer to understand environment structure. This will be more helpful when new person joins in the team to work on this type of developed environment. It will surely reduce the reamp-up time for engineer and can easily pick up the tasks to update/modify/enhance such type of test bench environments.
  3. Helps in maintenance, enhancement and for re-usability

Limitation (while naming meaningful name to class)

We cannot name class starting with numeric number like 0,1,2 etc.. ! Class name is not allowed to have numbers as first character. Meaning you can’t give a class name called “8_bit_dma_env” or “8bit_dma_env”. Simulation will throw an error if you use this approach, instead it can be defined like “eight_bit_dma_env” or “dma8_bit_env” this is allowed because you are not using numeric number as first character of class name.

Let’s take an example of small exercises to understand :

program ASIC_With_Ankit;

   class 1_byte_display_test;

   int a;
   byte awa = 8'hA5;

   task display ();

      $display ("Byte value =%h", awa);



initial begin
    1_byte_display_test  bdt;

     bdt = new ();
     bdt.display ();


Solution :

In above example, you can see the class name uses first character as numberic number “1” which is not allowed in system Verilog and when you try compiling this code, you will see an error given below. But if you try the same example with changing a name to “one_byte_display_test” or “byte1_display_test”, you would be able to compile the same exercises without error

#################### ERROR ######################
-- Compiling program ASIC_With_Ankit
** Error: near "1": syntax error, unexpected "INTEGER NUMBER", expecting "IDENTIFIER" or "TYPE_IDENTIFIER"

Hope this is useful information, keep reading “ASIC With Ankit” !

Enjoy !
ASIC With Ankit

Monday, October 20, 2014

Semiconductor Acquisistion - Mergers - Takeover and Impacts

Dear Readers,

Mergers and acquisition are common in today’s global market. If you take a history of any successful big companies in the market for more than 10-15 year, you would see the list of companies they acquired. So now two questions comes in mind. "Companies does acquisitions and become successful in the market? Or Successful companies does acquisition to be in market with profitable approach YoY?". There could be a different answers to these question depending upon various factors. I would be pleased to hear answers/views on these questions. Lets share views and experience.

Let’s assume that acquisition is part and process for successful companies and try to understand what impact does it make on different segments.

These days you might be observing industries’ various deals in terms of either merger, acquisition or takeover with all sets of new brand names. It is a way for companies to acquire technology, products and man power to improve profit and stock price while reducing overall expenses. In last few months, I have heard about many small to big acquisition in 2014. Some of them are given below in table and many more could be in the pipeline or in process.

Some of the recent acquisitions-mergers happened in 2014-15:

LSI - Broadcom
International Rectifier
LSI’s Flash business unit
ON Semiconductor
Aptina Imaging
Wilocity, Black Sand Tech, HP Patents and CSR plc

Lets understand what are the segments where mergers/acquisition could make an impact. There are two major segments where we could see the small to major impact because of acquisition and mergers.

1.       Service/consulting/Contract/Freelance
2.       Employees


Service segments who mostly relies on the product based companies for business revenue may face a challenge to gain business. During the merger/acquisition time most of the companies holds/stops their decisions for outsourcing their work to service companies. There are strong reason behind holding these decisions as they expect man power, technology and product acquisition as a part of merger/acquisition deal. So management has to think and restructure all sets of resources to make sure effective and profitable utilization model in place. Only after concluding this model they can either release, postpone, cancel their decision on outsource/contract the work. This could eventually effects service business revenue, consulting and contracting opportunities for freelancers. Would be happy to hear from experts on their views on real impact on service business !


During the merger acquisition process there are mostly/at-least two group of employees evolved, coming from the organization with different culture. In this transition phase, most of the employees faces challenges, especially on uncertain future, career. They would also be in phase where they think whose job is on critical edge ! This time frame is critical for employees as they need to make sure they are synced with other culture, people, style and way of work along with their individual performance !  Change is always difficult for employees especially they are not engaged in decision that impact their jobs and career. This could lead to a stress for individual and can impact on personal growth.

I had a talk with couple employees who were in same situation and got a smell that employees in this situation may fear losing their jobs or losing opportunities they had. These type of fear can negatively impact on productivity and eventually companies growth engine if continues. One more important point that I realize is “conflict with competitiveness”. When employees are in fear of losing jobs they are more likely to become competitive with others in the same path and eventually can end up having conflict. Competition is good if it is not creating violence !! J These could be major factors where employees gets affected during merger / acquisitions and would be happy to hear views experience from industry experts.

ASIC With Ankit

Monday, August 25, 2014

System Verilog Assertions (SVA) – Types, Usage, Advantages and Important Guidelines!!

ASICs continue to grow in size and complexities and in this case, traditional verification techniques are not sufficient to achieve verification confidence. In the complex designs, debugging simulations is an ever increasing challenge. To address these challenges assertion based verification is found. Design and Verification engineers can place assertions in design or bind to design which will be useful to monitor, report and take action when incorrect behavior is detected. Assertions are playing major role in test bench development which helps achieving maximum confidence on bug free design. Moreover it can be used in simulations as well as in formal verification.It enables engineers to leverage the strength for block level, subsystem level and for chip level verification in order to reduce the overall effort and efficient verification closure. System Verilog Assertions are setting up a viable and effective standard in the design and verification. An assertion adds an advantage in debugging process and makes complex simulation debug easy.

Below figure on block diagram gives brief idea on where we put the assertions in test bench development. As we can see assertion are placed on module boundaries to signals to monitor DUT interface

The introduction of SVA added the ability to perform immediate and concurrent assertions for Design as well as for Verification. Assertions are used to validate design whether it is working correctly or not. Assertions can be useful to make sure ‘How good is the test case?’ Furthermore, it provides a means to measure the quality of the verification process through the creation of coverage using cover property feature of System Verilog assertion.

In System Verilog there are two types of assertions:

Immediate Assertions

Immediate Assertion as name implies, execute immediately, in zero simulation time. It can be used in initial and always procedures, task and functions. This type of assertions performs a true/false. If the test result is true it executes the pass statement and if the test result is false or unknown, it executes false statement. Pass statements are optional; most engineers don’t prefer to specify pass statement as they are more interested on failures.

For example:

assert_xyx : assert (XYZ) $display (“Pass message”);

else $display (“Fail Message”);

Concurrent Assertions

A concurrent assertion uses a clock to trigger the assertions evaluation. Difference between concurrent and immediate assertions is that concurrent assertions evaluate condition over time, whereas immediate assertions test at the point in time when the assertion is called. This assertions can be specified in initial block, always block or standalone like continues assignment

For example:

property XYZ;

@(posedge clk) disable iff (!rst_n)

ABC |=> ## [0:10] (abc == xyz);

endproperty : XYZ

long_lable_p : assert property (XYZ);

else $error (“Error : failure message”);

long_lable_c : cover property (XYZ);

Assertion Advantages

  • Dozens of lines of code can be represented in one line using SVA code.
  • Assertions can be controlled and can be disabled at any point during the simulations. SVA can be turned off during the reset or until the simulation reaches the particular event or logic.
  • Assertion can have severity levels, failures can be non-fatal or fatal errors.
  • SVA can be ignored by synthesis; designer does not need to include translate_on and transalate_off throughout the RTL code.
  • Assertions can be used in simulation and formal verification.
  • An assertion helps in debugging the complex failure. Debugging using end-to-end checkers requires tracing the error from the external interface back to the source. In complex designs, debugging is almost impossible without the help of intermediate checkers. As assertions pinpoint errors at the source, they can be used as intermediate checkers and debugging can be made much easier and faster.
Who/Where should write assertions?

System Verilog is nothing but an extension of Verilog;it has everything to support Verilog with lots of new features for Verification as well as for design.Usually Verification engineers add assertions to a design after the HDL models have been written which means placing the assertions on module boundaries to signals within the model, or modifying the design models to insert assertions within the code.

Design Engineers can write assertion within a design while the HDL models are being coded. What type of assertions and scenario designer should provide within design need to decide before design work begins. Verification engineer define the assertion scenario during the test bench architecture. System Verilog assertions are mostly hooked up at the DUT interface level where it can continuously check protocol and functional activities.

Assertions controllability and why is it important?

Controllability is very important in Assertion design. There are two methods I called to control the assertions: You can also find the Assertion controlabilty blog post from "SVA Control Method" !

D Method (Dynamic Method)

Dynamic method is very popular where engineers required to control the assertion dynamically based on the test scenario they wants to execute. In today’s complex SoCs and their verification, Dynamic (D) method is popular as we regress the erroneous scenario to make sure DUT behaves accordingly. In this type of simulations engineers can dynamically switch on/off assertions.

System Verilog includes system calls for controlling the execution of assertions during simulations. There are three types of D Method.

1. $assertoff:This system function is used to disable all assertions but allows currently active assertions to complete before being disabled.
2 $asserton:This system function is used to turn all assertions back on
3. $assertkill: This system function used to kill and disable all assertions including currently active assertions.

By using $assertoff, the assertions specified as argument of this function will be turned off until a $asserton is executed. This way you can control assertions dynamically. Using these system tasks you can make your assertions dynamic and based on requirement we can make them enable or disable. Furthermore we can even kill using $assertkill.Dynamic control of Assertions can be used to turn off assertions during reset and initialization or during simulation erroneous protocol behavior.

S Method (Static Method):

To control assertion statically we can use System Verilog’s pre-processing capabilities. In this method assertions are generally ignored during the compilation phase w.r.t to `ifdef. This way we can build a different model by defining a different defines. Pre-processing defines can be applied to any place of the code and thus we can control the assertion as per need.



property XYZ (@posedge awa_clk);

a ##2 b;


XYZ_p : assert property (XYZ)

else $fatal (“ERROR : Failed message)


SVA proved to be a powerful assertion language; it provides several ways to control assertion. There are various reasons why assertions controllability is important, some important points are mentioned below:
  • To turn off assertions during reset and initialization or during simulation of erroneous protocol by doing this expected fails/checks can be turned off
  • Static control of assertions is used to speed up simulations time by turning off checks or to select appropriate assertion model for a given scenarios.
  • Dynamic method gives a control on when and where to start and stop/kill the assertions. It gives powerful controllability on simulation control
Coding Guidelines for SVA
  • Design code shall not repeated in assertions, it will not be efficient. By making sure not repetition concept, we can decide on use of concurrent or immediate assertions for assertion check. This can be done during the architectural phase of assertions.
  • Occurrence of “X” shall be checked explicitly, because “X” is implicitly mapped to “0”, which might hide a real assertion failure.
  • Make assertions message as clear as possible. This will help in debugging the assertions.
  • Disable the assertions during resets. Concurrent and Immediate assertions in combinational logic will begin executing at the start of the simulation, before reset and during reset design might not be in the known, stable state. Hundreds of false assertions can be reported during this phase and these false assertions could hide a real failure.
  • Assertion shall use the same clock as the design; otherwise synchronization will not work properly.
  • Assertion needs to consider the reset same as the design reset. This will avoid clock cycle offset which mostly produces illegal failure.
  • Name each assertion with meaningful naming convention; this will help in debugging the failure from the failure message and from the wave form display. If we don’t provide long meaning full ‘label’ to the assertion, only non-descriptive generic name will be displayed in the waveform. By looking at the wave engineers will be unable to identify the problem until they consult the original source code. By adding the long descriptive label, we can see the label name on wave itself and can be easily identify the assertion failure details.
  • Since the long label names are visible in waveform, it is good idea to use a label naming convention for each label with “ERROR_” followed by description of what the error message is if the assertion fails.
  • Use sequence layer as much as possible because sequences can be instantiated within the sequences and properties while properties can’t be instantiated in sequences.
  • Identify implementation specific corner cases using cover properties, this will help ensure DUT is exercised properly
Note : Same article is published on and can be found from here

Happy reading !
ASIC With Ankit

Saturday, April 12, 2014

Class - The Classic Feature - Part II

Dear AWA Readers

Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test bench development.  The usage of class is depends on the requirements.  Let’s understand what different types of classes that we use in system verilog.

Different types of classes:
  1. Basic Class
  2. Abstract Class
  3. Parameterised Class
  4. Nested Class
  5. Typedef Class

Basic Class:
Basic class is covered in my last post, you can refer It from here.

Abstract Class:

Classes without intending to create any objects of class are called Abstract classes.  These type of classes exists simply as a base class from which other classes can be derived. Virtual class is a temple or place holder for derived classes, abstract class is declared with a key word virtual

virtual class asic_with_ankit ;
virtual task awa1 ();
virtual task awa2 ();

Methods (tasks/functions) can be declared virtual, if methods are declared as virtual and is overwritten in derived class, return types, numbers and types of its arguments must be same as of virtual method. Virtual method defined in abstract class need not have body, In this case body will have to be defined in non virtual (non abstract) derived class.

Parameterised class

You might be knowing the parameterised modules in verilog/system verilog. Classes can also be parameterised in the same way that modules are. This type of class definition provides a template of an actual class, definition of actual class will be created at the time of class instantiation.
Placeholder/template for parameterized class

class  asic_with_ankit  # (parameter int A = 1);
     bit [A-1 : data];

Actual class will be created when you instantiate the class with parameter value

asic_with_ankit  #(8)    awa ;

Data type also possible to pass as an parameter.

Class asic_with_ankit  #(type A = bit);
     A   register_bit;
     task register_update  (A  reg_update);

Nested Class:
Definitions appear inside the definitions of another class as it were a member of other class. In system Verilog you are allowed to use class within another class. Class declarations nested inside a class scope are public and can be accessible outside of the class.
Nested class helps increasing encapsulations and lead to more readable and maintainable code.
class A; 
     class B; // Nested class for a node in a linked list. 
          bit [7:0] reg; 
Typedef Class
Sometimes a class variable needs to be declared before the class itself has been declared.

For example,
typedef class ASIC_With_Ankit;
     class  AWA;
          ASIC_With_Ankit   AWA1;

“typedef class ASIC_With_Ankit;”  : typedef of class ASIC_With_Ankit allows compiler to process the class before it uses inside the class  AWA. This will avoid the compilation error otherwise  compiler will flag an error.

Hope this will be useful information on understanding of different classes in system verilog and their usage.

Happy reading !